This invention relates to a semiconductor device with spare signal line circuits or so-called redundancy circuits for salvaging bits containing defective signal lines.
The yield of semiconductor devices such as memory devices like DRAMs usually becomes low if an attempt is made to increase their memory capacity by miniaturizing them, to make their production process more complicated or to increase their chip size. In order to prevent such a drop in the yield, it has been known to provide memory chips not only with the ordinary bit lines, word lines and memory cells but also with spare bit lines, word lines and memory cells or the so-called redundancy lines such that a defective component which is originally intended for use can be replaced by a spare component. A certain fraction of chips which would otherwise be deemed defective can be saved by such replacement before they are packaged. The conventional method of replacing a defective line has been to activate a spare bit line or word line, assigning thereto the same address as that of the defective line and to inactivate the bit line or word line of the defective bit.
FIG. 2 is a circuit diagram of a conventional redundancy circuit by way of which a static method of using redundancy lines is explained below. For the purpose of simplifying the explanation, 2-bit addresses are considered. In FIG. 2, bit lines originally intended for use are BIT11, BIT11-BIT14, BIT14 while BITR and BITR represent redundant bit lines. Let us now consider the situation where the pair of bit lines BIT11 and BIT11 is defective and to be replaced respectively by the redundancy bit lines BITR and BITR. First, the fuse FUSE11 is cut off in order to inactivate the bit lines BIT11 and BIT11. Since this cuts off the signals from the NAND gate NAND11, the voltage level at the node 20 becomes "H" because of the transistor TP6 with a small .beta. value while the node 21 becomes "L" through the inverter gate INV11. As a result, the bit lines BIT11 and BIT11 become disconnected forever electrically from the data lines D and D. Next, when the fuse FUSER5 is cut off in order to activate redundant lines corresponding to the bit lines BIT11 and BIT11, the node 22 becomes "H" similarly because of the transistor TP5 with a small .beta. value and the nodes 23 and 24 respectively become "L" and "H" such that all transistors TP11-TP14 and TN1-TN4 become transmissive and the address signals A.sub.0, A.sub.0, A.sub.1 and A.sub.1 are respectively transmitted to the nodes 25 and 26. In addition, the fuses FUSER2 and FUSER4 are cut off in order to eliminate the unwanted address signals A.sub.0 and A.sub.1 such that the bit lines BIT11 and BIT11 become inactive and redundant bit lines BITR and BITR become active.
A disadvantage associated with the circuit shown in FIG. 2 is that many large elements such as the fuses FUSER1-FUSER5 are required in the redundancy circuit. This means that the area on a chip occupied by the redundancy circuit becomes large and since a large number of fuses must be cut off according to the method of operation described above, a long time period is wasted in the replacement, resulting in an increase in the cost of the product.